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Si570/Si571
D OCUMENT C HANGE L IST
Revision 1.0 to Revision 1.1
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Added text to "3. Functional Description" on page 14,
paragraph 1, to state that the total output jitter
complies to and exceeds strict requirements of
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Restored programming constraint information on
page 15 and in Table 12, page 12.
various high-speed communication systems.
Revision 1.3 to Revision 1.4
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Clarified NC (No Connect) pin designations in Tables
13–14 on pages 22–23.
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Added Table 12, “Thermal Characteristics,” on
page 12.
Revision 1.1 to Revision 1.2
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Replaced “Unfreeze to Newfreq Delay” with the
clearer terminology “Unfreeze to Newfreq Timeout”
on page 15 and in Table 11 on page 12.
Added Freeze M procedure on page 14 for
preventing output clock changes during small
frequency change multi-register RFREQ writes.
Added Freeze M, Freeze VCADC, and RST_REG
versus RECALL information to Register 135
references in "4. Serial Port Registers" on pages 17
and 20.
Added Si570 20 ppm Total Stability Ordering Option
to Figure 6 on page 27.
Updated Figure 8 and Table 17 on page 29 to
include production test sidepads. This change is for
reference only as the sidepads are raised above the
seating plane and do not impact PCB layout.
Corrected errors in Table 10 on page 11.
Revision 1.2 to Revision 1.3
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Updated Table 3 on page 6 to include 7 ppm
temperature stability and 20 ppm to stability
parameters. Also changed aging test condition
(frequency drift over life) from 15 years to 20 years.
Updated 2.5 V/3.3 V and 1.8 V CML output level
specification for Table 4 on page 7.
Added footnotes clarifying max offset frequency test
conditions in Table 5 on page 8.
Updated ESD HBM sensitivity rating and the JEDEC
standard in Note 2 in Table 13 on page 13.
Updated Table 10 on page 11 to include "Moisture
Sensitivity Level" and "Contact Pads" rows.
Added Si570 7 ppm Total Stability Ordering Option to
Figure 6 on page 27.
Updated Figure 7 and Table 16 on page 28 to reflect
specific marking information. Previously, Figure 7
was generic.
Clarified "3.1.2. Reconfiguring the Output Clock for
Large Changes in Output Frequency" on page 15
and added new registers 13-18 in "4. Serial Port
Registers" on page 18 for the Si570 7 ppm
temperature stability / 20 ppm total stability ordering
option.
Rev. 1.4
31
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